Owing to the large scale integration of electronic circuits the error proneness and the error rate in electronic circuits are increasing so that, in particular, for security-critical applications the circuits are increasingly doubled or doubled so as to be inverted or are realized in so-called “two rail” logic. Then the outputs of the doubled circuits or the circuits that are doubled so as to be inverted are compared in a unit that is called the comparator. In the event of a disparity the signals that are to be compared generate an error signal. If the outputs that are doubled so as to be inverted are compared, such a comparator is called the “two rail tester” or “two rail checker”. A “two rail checker” sends an error signal, if the signals to be compared are not inverted (bit-by-bit) in relation to each other. In the event of error-free, identical signals a faulty output signal will indicate only that there is some kind of difference in the two input signals. At the same time the noisy bit position cannot be inferred, a state that is a drawback.
If there are errors in the comparator, it can happen that the faulty comparator cannot indicate, for example, any errors that may occur in the circuits to be compared, a feature that must be ruled out, in particular, in security-critical applications. Therefore, an important goal to be achieved in the design of comparators is that internal errors of the comparator are detected during continuous operation. If a comparator compares two signals, which are identical in the error-free case, then as long as no errors occur in the circuits to be monitored, the same input values are always present at the two inputs of the comparator. Hence, the number of possible input values for the comparator is very limited, in particular to the input values that are identical at both inputs of the comparator. For specific circuits that are to be compared, the number of possible input values for the comparator is even smaller, since of the circuits to be monitored only a subquantity of the output values that are possible in principle is generated.
Therefore, the problem that must be solved when designing a comparator is to detect the maximum number of internal errors of the comparator when the minimum number of correct input values (that is, the same input values or input values that are inverted bit-by-bit in relation to each other) are available at the output of the comparator. Furthermore, the object is also to be able to test any non-detected errors at a low cost. When two signals are compared, one must make eventually a binary decision—0 or 1—whether these signals are identical or not. Therefore, comparators with a binary output are especially interesting.
For such comparators it is especially important that any error, occurring at its output, for example, a “stuck at”—0/1 error—is easily detected or easily tested, since in the event of such an error no other error in the circuits or the signals to be compared can be detected. There exists a comparator with one output, as described, for example, by Kusko, M. al.: “99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor”, Proc. ITC, pp. 586-592, 2001. The identical signals to be compared in the error-free case are wired XNOR to XNOR gates by means of components; and the outputs of the FOR signals are wired AND to an error signal. In the absence of errors the outputs of the XNOR gates are equal to 1. A value 0 at an output of at least one NOR gate indicates an error. If an error occurs in the input signals to be compared, then the comparator sends the value 0; and in the absence of errors the value 1 is sent. The drawback with this comparator is that the test of the possible errors is time intensive and demands, in particular, a large number of test inputs, as described by Kusko, M. et al. In particular, it is difficult to detect a “stuck at 1” error at the output, since the two inputs of the comparator are connected to the outputs of identical circuits, which in the absence of errors send the same values, which always give a reason for an output 1 of the comparator.
In order to improve the testability of the comparator, Kundu, S. et al.: “Self-checking Comparator with one Periodic Output”, IEEE Trans. Comp., Vol. 45, pp. 379-380, 1996, suggest a comparator with one periodic output, which also indicates its internal errors during continuous operation in that the output is not periodic. The drawback with this comparator is that a special CMOS element has to be used that is not available especially if the comparator is supposed to be designed with a commercially available design tool. Another drawback—especially at very high clock rates—is the high energy consumption as a result of the periodic and dynamic behavior of the comparator as well as the non-static output.
Other comparators with a non-static periodic output are described, for example, in Metra, C. et al.: “Highly Testable and Compact Single Output Comparator”, Proc. VLSI Test Symposium, pp. 210-215, 1997, and Matakias, S. et al.: “Ultra Fast and Low Cost Parallel Two Rail Checker Targeting High Fan-In Applications”, IEEE CS Annual Symposium on VLSI(ISVLSI), pp. 293-296, 2004. Even these comparators require special elements, which usually cannot be realized with a commercial design tool; and they exhibit a periodic, non-static output, features that constitute a drawback.